References: 1] Random number generation (2013). Available. en.wikipedia.org/wiki/Random_number_generation. [2] Wijesinghe, W.A.S., Jayananda, M.K. & Sonnadara, D.U.J. (2006) Hardware implementation of random number generators. Proceedings of the Technical Sessions. Available at www.ip-sl.org/procs/ipsl063.pdf. Mart 2013, Vol. 22. Institute of Physics: Sri Lanka, pp. 25–36. [3] Design for Testability, Laung-Terng (L.-T.) Wang, Chapter 3 Electronic design automation: Synthesis, verification, and test. In: (edited by L.-T. Wang, Y.-W. Chang & K.-T. (T.) Cheng). Morgan Kaufmann Publishers: Burlington, MA, USA, pp. 97–172. [4] Jha, N. & Gupta, S. (2003). Testing of Digital Systems. Cambridge University Press: Cambridge. [5] Nas, R.J.M. & van Berkel, C.H. (2010) High throughput, low setup time, reconfigurable linear feedback shift registers, IEEE international conference on computer design (ICCD), pp. 31–37. [6] Ahmed, N., Tehranipour, M.H. & Nourani, M. (2004) Low power pattern generation for BIST architecture. Proceedings of the 2004 International Symposium on Circuits and Systems (ISCAS’04), Vol. 2, pp. 689–692. [7] Bezerra, E.A., Vargas, F. & Gough, M.P. (2001) Improving reconfigurable systems reliability by combining periodical test and redundancy techniques: A case study. Journal of Electronic Testing, 17, 163–174 [DOI: 10.1023/A:1011177911388]. [8] Jhansirani, A., Harikishore, K., Basha, F.N., Poornima, J., Jyothil, M., Sahithi, M. & Srinivas, P. (2012) Fault tolerance in bit swapping LFSR using FPGA architecture. International Journal of Engineering Research and Applications, 2, 1080–1087. [9] Lowy, M. (1966) Parallel implementation of Linera Feedback Shift Registers for low power applications. IEEE Transactions on Circuits and Systems. Part II: Analog and Digital Signal Processing, 43, 458–466. [10] Hamid, M.E. & Chen, C.-I.H. (1998) A note to low-power linear feedback shift registers. IEEE Transactions on Circuits and Systems II (trans. IEEE), 45, 1304–1307 [DOI: 10.1109/82.718599]. |