Journal of Information Organization


Vol No. 14 ,Issue No. 1 2024

Formal Verif ication of Systemc Using Error-Free Translation
Claude Helmstetter
Verimag – CNRS 2 Avenue de Vignate, 38610 Gières, France
Abstract: SystemC/TLMs are C++ programs that simulate embedded software before the hardware low-level description is available and are used as gold-plated models for hardware verification. Verification of SystemC/TLMs is important because a mistake in the model can deceive the system designers or reveal a defect in the specifications. There is an open-source simulator, but there are no formal verification tools. To apply model checking to System-C/TML models, you must provide semantics for standard C++ code and specific System-C/TML features. The usual approach is translating the SystemC/TML code into a formal language with a model checker. However, we suggest a different approach that eliminates the risk of error-prone translation. In the case of a system-C/TML program, transitions are obtained by running the original code using G++ and an extended systemC library. We ask the user to provide additional functions to store the current model state.These extra functions are typically less than 20% larger than the original model and allow applying all CADP verification capabilities to the SystemC/TLM model.
Keywords: Systemc/TML Code, Formal Verification Procedures, Model Checkers Formal Verif ication of Systemc Using Error-Free Translation
DOI:https://doi.org/10.6025/jio/2024/14/1/1-18
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