Attention Message Passing Network for Intelligent Electronic Circuit Topology Analysis
Maleerat Maliyaem
Journal of Electronic Systems, Vol. 16, No. 2, 2026.
DOI: https://doi.org/10.6025/jes/2026/16/2/98-123
Link: https://www.dline.info/jes/fulltext/v16n2/jesv16n2_3.pdf
Abstract:
The increasing complexity of modern electronic systems has created a growing demand for intelligent
Electronic Design Automation (EDA) frameworks capable of understanding circuit topology, signal
propagation, and component interaction behavior. Traditional machine learning approaches are limited in
capturing the non-Euclidean structural relationships inherent in electronic circuits because they operate
primarily on independent feature vectors rather than connectivity aware representations. This study presents
a graph-based analytical framework for intelligent circuit understanding using a Heterogeneous Graph
Attention Message Passing Network (HGAMPN). The proposed framework combines heterogeneous graph
representation, Message Passing Neural Networks (MPNNs), Graph Attention Networks (GATs), hierarchical
graph pooling, and explainable artificial intelligence mechanisms to model connectivity behavior, signal
propagation, component dependencies, and hierarchical design structures within electronic circuits.
The dataset employed in this study consists of structured circuit topology data obtained from the Kaggle
Electronic Circuit for Machine Learning dataset. The dataset contains component level and connectivitylevel
information describing electronic circuits composed of resistors, capacitors, transistors, diodes, LEDs,
voltage sources, switches, and sensor elements. Each circuit is represented through structured metadata
including component identifiers, component categories, pin level relationships, electrical values, and netbased
interconnections. This representation enables the reconstruction of circuit structures as heterogeneous
graphs where components and nets are modeled as nodes and electrical interconnections are represented asedges.
The proposed framework demonstrates how graph-based learning architectures can capture circuit
connectivity patterns, identify dominant signal propagation pathways, and discover hierarchical functional
modules within electronic systems. The study further illustrates how explainable graph learning mechanisms
can identify salient subgraphs, influential electrical paths, and critical component interactions. The resulting
framework provides a strong foundation for intelligent EDA, autonomous circuit understanding, graphbased
hardware learning, and explainable AI-driven electronic system analysis.