The Research of Correlation Power Analysis on a AES Implementations
Noura Benhadjyoussef, Mohsen Machhout and Rached Tourki
Journal of Intelligent Computing, Vol. 2, No. 3, 2011.
DOI: 
Link: http://www.dline.info/jic/fulltext/v2n3/1.pdf
Abstract:
Among various side-channel attacks, power analysis pose a serious threat to the security of different cryptographic implementations such as Simple Power Analysis (SPA), Differential Power Analysis (DPA) and Correlation Power Analysis (CPA). Such attacks typically involve representing the relationship between the instantaneous power consumption of a device executing a cryptographic algorithm, and certain intermediate data handled. In the present paper, we conduct a simulation-based correlation power attack and we demonstrate the experimental procedure of this attack against AES using two different devices: Xilinx Virtex TM-5 FPGA (XC5VLX30) and 8051-compatible microcontroller. The experimental results show that the AES hardware implementations have better resistance against power attack and the validity of power model used to calculate hypothetical power depends statistically on the implementation.