01621nas a2200193   4500008004100000245009000041210006900131260000900200300001400209490000600223520095500229653001901184653001901203653003301222653002901255100001201284700001401296856011701310       2011                        eng d00aThe design and challenges of online reprogramming system for wireless sensor networks0 adesign and challenges of online reprogramming system for wireles  c2011  a255 - 2600 v93 aAt present, the online network reprogramming faces two challenges: 1) How to save the energy consumed during the code dissemination; and 2) How to enhance the security of online network reprogramming. In this paper, we modify the work flow of online reprogramming system and separates an alone reprogramming component from the whole program image which need not be transmitted in order to reduce the energy consumption. According to the security vulnerabilities in the image management aspects of code dissemination, acipher puzzle-based image management algorithm is proposed. According to the based-request attacks, several counter measures are introduced in our online reprogramming system, such as secure broadcast authentication based on cluster keys and the request count technique. By integrating several key techniques, our online reprogramming system can securely and energy-efficiently disseminate the new program image into the whole WSNs.10aAuthentication10aHash Key Chain10aOnline Network Reprogramming10aWireless sensor networks1 aXie, M.1 aZhang, G.  uhttp://www.scopus.com/inward/record.url?eid=2-s2.0-84855387891&partnerID=40&md5=a4ce74298f75f1a849cd6ed7c203d24f01641nas a2200181   4500008004100000245011600041210006900157260000900226300001400235490000600249520098800255653002701243653003101270653001501301100001401316700001201330856011701342       2011                        eng d00aThe design and implementation of the digital down converter based on the improved dds and dspbuilder techniques0 adesign and implementation of the digital down converter based on  c2011  a281 - 2860 v93 aDDC (Digital Down Converter), as a key part of digital receivers, aims to get low-speed digital baseband signals by extracting and filtering the digital signals transformed by high-speed ADC (Analog Digital Conversion). This paper employs the multi-rate process technique to design the DDC, i.e. firstly conducting data CIC (Cascade Integrator Comb) extraction, then HBF (Half-Band Filtering) and at last low pass filtering. CIC, which doesn't need multiplication, can realize high speed filtering and the HBF has high operation efficiency and good realtime performance. FPGA realization is taken into full consideration during the project design of the top. In the end, this paper adopts the Simulink instrument in MATLAB and combines Altera's signal processing toolbox-DSPBuilder to implement the design scheme by the FPGA. It focuses on the description of FPGA implementation of the digitally controlled oscillator, CIC filter, half-band extracting filter and the low pass filter.10aDigital Down Converter10aDirect Digital Synthesizer10aDSPBuilder1 aZhang, G.1 aXie, M.  uhttp://www.scopus.com/inward/record.url?eid=2-s2.0-84855395419&partnerID=40&md5=64afa914e4030e52506b12f1d4b5d816